行业:IT|通信|电子|互联网
职位:电子技术/半导体/集成电路
部门:
人数:若干
地区:北京
性质:全职
性别:不限
婚姻:不限
学历:本科
经验:不限
年龄:不限年龄
待遇:面议
内部培训 五险一金 工作环境好 弹性工作制 年终多薪
仅限于2018年毕业的学生​
Job title: Engineering - Hardware - Digital IC Design- Participate in high performance noise predictive iterative read channel design
- Will be involved in the whole ASIC design flow from RTL coding through P&R support, which includes logic design, DFT planning and implementation, logic synthesis, power optimization, static timing analysis and sign-off.


- Major in EE, CS or related, Master Degree with 2+ years or Bachelor with 5+ years working experiences in ASIC design or verification.
- Familiar with Verilog and RTL design
- Familiar with System-Verilog and UVM verification methodology
- Familiar with script languages(perl,tcl,sh etc.) is a plus
- Familiar with digital signal processing knowledge is a plus
- Good problem solving and communication skills
- Good written and spoken English. Be able to work together with global team.